High IP3 Mixer, 5 - 33 GHz

This passive mixer “engine” is designed for more linear applications such as high bit rate transmitters and receivers. The mixer integrates a single ended cold FET structure and diplexer for about 9 dB of conversion loss with a +22 dBm IIP3.This device can be used for upconversion or downconversion in upper sideband or lower sideband configurations. Two of these mixers can be used in a quadrature configuration as an image rejection mixer. Positive bias voltage (<1v) can be applied to the LO or the Vg (opt) pin to reduce LO drive requirements. The Vg pin is internally bypassed. Positive bias voltage (<1v) can also be applied to the IF pin to optimize device linearity. This mixer is targeted for higher data rate systems such as P2P, Satcom and LAN.