S28115
100Gbps Multi-Link Gearbox
The S28115 Multi-Link Gearbox PHY extends the PHY product family into virtual link aggregation and 10GBASE-R port expansion. The MLG allows up to ten independent 10GBASE-R links to be carried across a 4 x 25 Gbps interface either across a fiber-efficient 100GBASE-R4 link or to interface with a 4 x 25 Gbps next generation switch or network processor unit. Equally suited for data center switches, routers and optical modules, the S28115 benefits from superior electrical performance and enhanced diagnostic features to accelerate chip bring-up and debug at the system level. Integrated 100G mux/demux facilitates transport of up to 10 x 10GE over a 4 x 25G physical interface.
Product Specifications
- Part Number
- S28115
- Description
- 100Gbps Multi-Link Gearbox
- Signals & Rate
- OTU4, 100GE, 10GE
- Max Data Rate(Gbps)
- 28.000
- Signal Modulation Format
- NRZ
- I/F Spec
- CAUI-4, CPPI, XLPPI, XFI, SFI, OTL4.10, OTL 4.4
- Package
- 19mm 324-pin HFCBGA
Features
- XFI and SFP+ compliant 10-lane host interface
- OIF CEI-28G-SR compliant module interface
- OIF MLG 1.0 compliant in-band coding
- IEEE 802.3 Clause 49 compliant PCS on each 10GE input and output lane
- Provisionable lane alignment marker insertion in the MLG mux
- Provisionable lane physical lane assignment in the MLG demux
- 3-Tap Transmit FIR (pre and post-cursor emphasis) on all 10G and 28G transmitters
- Programmable 28 Gbps output voltage to over 800mVpp
- Integrated CTLE and limiting amp on 10G and 28G receivers
- Receive eye monitors for in service link margin evaluation and receiver optimization
- Virtual lane identification and BIP error reporting
- Reference clock at 1/16th, 1/32nd or 1/64th the host interface rate
- Flexible timing modes including reference timing and recovered clock timing
- Up to 6 optional clock outputs from any internal clock source